mer jan 19 11:11:30 CET 2011 %%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%% % Results for PodWR/X01.litmus % %%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%% PPC X01 "reference, one thread" {0:r2=y; 0:r4=x;} P0 ; li r1,1 ; stw r1,0(r2) ; lwz r3,0(r4) ; locations [0:r3; ] forall (true) Generated assembler _litmus_P0_0_: b Lit__L1 _litmus_P0_1_: Lit__L0: _litmus_P0_2_: li 11,1 _litmus_P0_3_: stw 11,0(28) _litmus_P0_4_: lwz 31,0(8) _litmus_P0_5_: addi 10,10,-1 _litmus_P0_6_: Lit__L1: _litmus_P0_7_: cmpwi 10,0 _litmus_P0_8_: bgt Lit__L0 Test X01 Required Histogram (1 states) 1 :>0:r3=0; Ok Witnesses Positive: 1, Negative: 0 Condition forall (true) is validated Hash=9e40fd38b80077594cd525bc6de73f1d Observation X01 Always 1 0 Time X01 0.13 %%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%% % Results for PodWR/X02.litmus % %%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%% PPC X02 "PodWR Fre PodWR Fre" {0:r2=y; 0:r4=x; 1:r2=x; 1:r4=y;} P0 | P1 ; li r1,1 | li r1,1 ; stw r1,0(r2) | stw r1,0(r2) ; lwz r3,0(r4) | lwz r3,0(r4) ; exists (0:r3=0 /\ 1:r3=0) Generated assembler _litmus_P1_0_: b Lit__L3 _litmus_P1_1_: Lit__L2: _litmus_P1_2_: li 11,1 _litmus_P1_3_: stw 11,0(8) _litmus_P1_4_: lwz 31,0(28) _litmus_P1_5_: addi 10,10,-1 _litmus_P1_6_: Lit__L3: _litmus_P1_7_: cmpwi 10,0 _litmus_P1_8_: bgt Lit__L2 _litmus_P0_0_: b Lit__L1 _litmus_P0_1_: Lit__L0: _litmus_P0_2_: li 11,1 _litmus_P0_3_: stw 11,0(28) _litmus_P0_4_: lwz 31,0(8) _litmus_P0_5_: addi 10,10,-1 _litmus_P0_6_: Lit__L1: _litmus_P0_7_: cmpwi 10,0 _litmus_P0_8_: bgt Lit__L0 Test X02 Allowed Histogram (1 states) 1 :>0:r3=1; 1:r3=1; No Witnesses Positive: 0, Negative: 1 Condition exists (0:r3=0 /\ 1:r3=0) is NOT validated Hash=e3d8acee19f171034e75984cc2f0ce68 Observation X02 Never 0 1 Time X02 0.57 %%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%% % Results for PodWR/X03.litmus % %%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%% PPC X03 "PodWR Fre PodWR Fre PodWR Fre" {0:r2=z; 0:r4=x; 1:r2=x; 1:r4=y; 2:r2=y; 2:r4=z;} P0 | P1 | P2 ; li r1,1 | li r1,1 | li r1,1 ; stw r1,0(r2) | stw r1,0(r2) | stw r1,0(r2) ; lwz r3,0(r4) | lwz r3,0(r4) | lwz r3,0(r4) ; exists (0:r3=0 /\ 1:r3=0 /\ 2:r3=0) Generated assembler _litmus_P1_0_: b Lit__L3 _litmus_P1_1_: Lit__L2: _litmus_P1_2_: li 11,1 _litmus_P1_3_: stw 11,0(7) _litmus_P1_4_: lwz 30,0(8) _litmus_P1_5_: addi 10,10,-1 _litmus_P1_6_: Lit__L3: _litmus_P1_7_: cmpwi 10,0 _litmus_P1_8_: bgt Lit__L2 _litmus_P0_0_: b Lit__L1 _litmus_P0_1_: Lit__L0: _litmus_P0_2_: li 11,1 _litmus_P0_3_: stw 11,0(28) _litmus_P0_4_: lwz 30,0(8) _litmus_P0_5_: addi 10,10,-1 _litmus_P0_6_: Lit__L1: _litmus_P0_7_: cmpwi 10,0 _litmus_P0_8_: bgt Lit__L0 _litmus_P2_0_: b Lit__L5 _litmus_P2_1_: Lit__L4: _litmus_P2_2_: li 11,1 _litmus_P2_3_: stw 11,0(8) _litmus_P2_4_: lwz 30,0(28) _litmus_P2_5_: addi 10,10,-1 _litmus_P2_6_: Lit__L5: _litmus_P2_7_: cmpwi 10,0 _litmus_P2_8_: bgt Lit__L4 Test X03 Allowed Histogram (1 states) 1 :>0:r3=1; 1:r3=1; 2:r3=1; No Witnesses Positive: 0, Negative: 1 Condition exists (0:r3=0 /\ 1:r3=0 /\ 2:r3=0) is NOT validated Hash=2386f60ec2909f986d6ca30d5506ce7d Observation X03 Never 0 1 Time X03 0.17 %%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%% % Results for PodWR/X04.litmus % %%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%% PPC X04 "PodWR Fre PodWR Fre PodWR Fre PodWR Fre" {0:r2=a; 0:r4=x; 1:r2=x; 1:r4=y; 2:r2=y; 2:r4=z; 3:r2=z; 3:r4=a;} P0 | P1 | P2 | P3 ; li r1,1 | li r1,1 | li r1,1 | li r1,1 ; stw r1,0(r2) | stw r1,0(r2) | stw r1,0(r2) | stw r1,0(r2) ; lwz r3,0(r4) | lwz r3,0(r4) | lwz r3,0(r4) | lwz r3,0(r4) ; exists (0:r3=0 /\ 1:r3=0 /\ 2:r3=0 /\ 3:r3=0) Generated assembler _litmus_P1_0_: b Lit__L3 _litmus_P1_1_: Lit__L2: _litmus_P1_2_: li 11,1 _litmus_P1_3_: stw 11,0(7) _litmus_P1_4_: lwz 31,0(8) _litmus_P1_5_: addi 10,10,-1 _litmus_P1_6_: Lit__L3: _litmus_P1_7_: cmpwi 10,0 _litmus_P1_8_: bgt Lit__L2 _litmus_P0_0_: b Lit__L1 _litmus_P0_1_: Lit__L0: _litmus_P0_2_: li 11,1 _litmus_P0_3_: stw 11,0(7) _litmus_P0_4_: lwz 31,0(8) _litmus_P0_5_: addi 10,10,-1 _litmus_P0_6_: Lit__L1: _litmus_P0_7_: cmpwi 10,0 _litmus_P0_8_: bgt Lit__L0 _litmus_P3_0_: b Lit__L7 _litmus_P3_1_: Lit__L6: _litmus_P3_2_: li 11,1 _litmus_P3_3_: stw 11,0(28) _litmus_P3_4_: lwz 31,0(8) _litmus_P3_5_: addi 10,10,-1 _litmus_P3_6_: Lit__L7: _litmus_P3_7_: cmpwi 10,0 _litmus_P3_8_: bgt Lit__L6 _litmus_P2_0_: b Lit__L5 _litmus_P2_1_: Lit__L4: _litmus_P2_2_: li 11,1 _litmus_P2_3_: stw 11,0(8) _litmus_P2_4_: lwz 31,0(28) _litmus_P2_5_: addi 10,10,-1 _litmus_P2_6_: Lit__L5: _litmus_P2_7_: cmpwi 10,0 _litmus_P2_8_: bgt Lit__L4 Test X04 Allowed Histogram (1 states) 1 :>0:r3=1; 1:r3=1; 2:r3=1; 3:r3=1; No Witnesses Positive: 0, Negative: 1 Condition exists (0:r3=0 /\ 1:r3=0 /\ 2:r3=0 /\ 3:r3=0) is NOT validated Hash=20d1d70975910f92f72e65b74ff2dc00 Observation X04 Never 0 1 Time X04 0.26 %%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%% % Results for PodWR/X05.litmus % %%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%% PPC X05 "PodWR Fre PodWR Fre PodWR Fre PodWR Fre PodWR Fre" {0:r2=b; 0:r4=x; 1:r2=x; 1:r4=y; 2:r2=y; 2:r4=z; 3:r2=z; 3:r4=a; 4:r2=a; 4:r4=b;} P0 | P1 | P2 | P3 | P4 ; li r1,1 | li r1,1 | li r1,1 | li r1,1 | li r1,1 ; stw r1,0(r2) | stw r1,0(r2) | stw r1,0(r2) | stw r1,0(r2) | stw r1,0(r2) ; lwz r3,0(r4) | lwz r3,0(r4) | lwz r3,0(r4) | lwz r3,0(r4) | lwz r3,0(r4) ; exists (0:r3=0 /\ 1:r3=0 /\ 2:r3=0 /\ 3:r3=0 /\ 4:r3=0) Generated assembler _litmus_P1_0_: b Lit__L3 _litmus_P1_1_: Lit__L2: _litmus_P1_2_: li 11,1 _litmus_P1_3_: stw 11,0(7) _litmus_P1_4_: lwz 30,0(8) _litmus_P1_5_: addi 10,10,-1 _litmus_P1_6_: Lit__L3: _litmus_P1_7_: cmpwi 10,0 _litmus_P1_8_: bgt Lit__L2 _litmus_P0_0_: b Lit__L1 _litmus_P0_1_: Lit__L0: _litmus_P0_2_: li 11,1 _litmus_P0_3_: stw 11,0(7) _litmus_P0_4_: lwz 30,0(8) _litmus_P0_5_: addi 10,10,-1 _litmus_P0_6_: Lit__L1: _litmus_P0_7_: cmpwi 10,0 _litmus_P0_8_: bgt Lit__L0 _litmus_P4_0_: b Lit__L9 _litmus_P4_1_: Lit__L8: _litmus_P4_2_: li 11,1 _litmus_P4_3_: stw 11,0(7) _litmus_P4_4_: lwz 30,0(8) _litmus_P4_5_: addi 10,10,-1 _litmus_P4_6_: Lit__L9: _litmus_P4_7_: cmpwi 10,0 _litmus_P4_8_: bgt Lit__L8 _litmus_P3_0_: b Lit__L7 _litmus_P3_1_: Lit__L6: _litmus_P3_2_: li 11,1 _litmus_P3_3_: stw 11,0(28) _litmus_P3_4_: lwz 30,0(8) _litmus_P3_5_: addi 10,10,-1 _litmus_P3_6_: Lit__L7: _litmus_P3_7_: cmpwi 10,0 _litmus_P3_8_: bgt Lit__L6 _litmus_P2_0_: b Lit__L5 _litmus_P2_1_: Lit__L4: _litmus_P2_2_: li 11,1 _litmus_P2_3_: stw 11,0(8) _litmus_P2_4_: lwz 30,0(28) _litmus_P2_5_: addi 10,10,-1 _litmus_P2_6_: Lit__L5: _litmus_P2_7_: cmpwi 10,0 _litmus_P2_8_: bgt Lit__L4 Test X05 Allowed Histogram (1 states) 1 :>0:r3=1; 1:r3=1; 2:r3=1; 3:r3=1; 4:r3=1; No Witnesses Positive: 0, Negative: 1 Condition exists (0:r3=0 /\ 1:r3=0 /\ 2:r3=0 /\ 3:r3=0 /\ 4:r3=0) is NOT validated Hash=0e7f48017984896cb3bbf78c1621c4fb Observation X05 Never 0 1 Time X05 0.33 %%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%% % Results for PodWR/X06.litmus % %%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%% PPC X06 "PodWR Fre PodWR Fre PodWR Fre PodWR Fre PodWR Fre PodWR Fre" {0:r2=c; 0:r4=x; 1:r2=x; 1:r4=y; 2:r2=y; 2:r4=z; 3:r2=z; 3:r4=a; 4:r2=a; 4:r4=b; 5:r2=b; 5:r4=c;} P0 | P1 | P2 | P3 | P4 | P5 ; li r1,1 | li r1,1 | li r1,1 | li r1,1 | li r1,1 | li r1,1 ; stw r1,0(r2) | stw r1,0(r2) | stw r1,0(r2) | stw r1,0(r2) | stw r1,0(r2) | stw r1,0(r2) ; lwz r3,0(r4) | lwz r3,0(r4) | lwz r3,0(r4) | lwz r3,0(r4) | lwz r3,0(r4) | lwz r3,0(r4) ; exists (0:r3=0 /\ 1:r3=0 /\ 2:r3=0 /\ 3:r3=0 /\ 4:r3=0 /\ 5:r3=0) Generated assembler _litmus_P1_0_: b Lit__L3 _litmus_P1_1_: Lit__L2: _litmus_P1_2_: li 11,1 _litmus_P1_3_: stw 11,0(7) _litmus_P1_4_: lwz 30,0(8) _litmus_P1_5_: addi 10,10,-1 _litmus_P1_6_: Lit__L3: _litmus_P1_7_: cmpwi 10,0 _litmus_P1_8_: bgt Lit__L2 _litmus_P0_0_: b Lit__L1 _litmus_P0_1_: Lit__L0: _litmus_P0_2_: li 11,1 _litmus_P0_3_: stw 11,0(7) _litmus_P0_4_: lwz 30,0(8) _litmus_P0_5_: addi 10,10,-1 _litmus_P0_6_: Lit__L1: _litmus_P0_7_: cmpwi 10,0 _litmus_P0_8_: bgt Lit__L0 _litmus_P5_0_: b Lit__L11 _litmus_P5_1_: Lit__L10: _litmus_P5_2_: li 11,1 _litmus_P5_3_: stw 11,0(7) _litmus_P5_4_: lwz 30,0(8) _litmus_P5_5_: addi 10,10,-1 _litmus_P5_6_: Lit__L11: _litmus_P5_7_: cmpwi 10,0 _litmus_P5_8_: bgt Lit__L10 _litmus_P4_0_: b Lit__L9 _litmus_P4_1_: Lit__L8: _litmus_P4_2_: li 11,1 _litmus_P4_3_: stw 11,0(7) _litmus_P4_4_: lwz 30,0(8) _litmus_P4_5_: addi 10,10,-1 _litmus_P4_6_: Lit__L9: _litmus_P4_7_: cmpwi 10,0 _litmus_P4_8_: bgt Lit__L8 _litmus_P3_0_: b Lit__L7 _litmus_P3_1_: Lit__L6: _litmus_P3_2_: li 11,1 _litmus_P3_3_: stw 11,0(28) _litmus_P3_4_: lwz 30,0(8) _litmus_P3_5_: addi 10,10,-1 _litmus_P3_6_: Lit__L7: _litmus_P3_7_: cmpwi 10,0 _litmus_P3_8_: bgt Lit__L6 _litmus_P2_0_: b Lit__L5 _litmus_P2_1_: Lit__L4: _litmus_P2_2_: li 11,1 _litmus_P2_3_: stw 11,0(8) _litmus_P2_4_: lwz 30,0(28) _litmus_P2_5_: addi 10,10,-1 _litmus_P2_6_: Lit__L5: _litmus_P2_7_: cmpwi 10,0 _litmus_P2_8_: bgt Lit__L4 Test X06 Allowed Histogram (1 states) 1 :>0:r3=1; 1:r3=1; 2:r3=1; 3:r3=1; 4:r3=1; 5:r3=1; No Witnesses Positive: 0, Negative: 1 Condition exists (0:r3=0 /\ 1:r3=0 /\ 2:r3=0 /\ 3:r3=0 /\ 4:r3=0 /\ 5:r3=0) is NOT validated Hash=742243f7ac102ff7a48ebf2a880bf66b Observation X06 Never 0 1 Time X06 1.18 %%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%% % Results for PodWR/X07.litmus % %%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%% PPC X07 "PodWR Fre PodWR Fre PodWR Fre PodWR Fre PodWR Fre PodWR Fre PodWR Fre" {0:r2=d; 0:r4=x; 1:r2=x; 1:r4=y; 2:r2=y; 2:r4=z; 3:r2=z; 3:r4=a; 4:r2=a; 4:r4=b; 5:r2=b; 5:r4=c; 6:r2=c; 6:r4=d;} P0 | P1 | P2 | P3 | P4 | P5 | P6 ; li r1,1 | li r1,1 | li r1,1 | li r1,1 | li r1,1 | li r1,1 | li r1,1 ; stw r1,0(r2) | stw r1,0(r2) | stw r1,0(r2) | stw r1,0(r2) | stw r1,0(r2) | stw r1,0(r2) | stw r1,0(r2) ; lwz r3,0(r4) | lwz r3,0(r4) | lwz r3,0(r4) | lwz r3,0(r4) | lwz r3,0(r4) | lwz r3,0(r4) | lwz r3,0(r4) ; exists (0:r3=0 /\ 1:r3=0 /\ 2:r3=0 /\ 3:r3=0 /\ 4:r3=0 /\ 5:r3=0 /\ 6:r3=0) Generated assembler _litmus_P1_0_: b Lit__L3 _litmus_P1_1_: Lit__L2: _litmus_P1_2_: li 11,1 _litmus_P1_3_: stw 11,0(7) _litmus_P1_4_: lwz 30,0(8) _litmus_P1_5_: addi 10,10,-1 _litmus_P1_6_: Lit__L3: _litmus_P1_7_: cmpwi 10,0 _litmus_P1_8_: bgt Lit__L2 _litmus_P0_0_: b Lit__L1 _litmus_P0_1_: Lit__L0: _litmus_P0_2_: li 11,1 _litmus_P0_3_: stw 11,0(7) _litmus_P0_4_: lwz 30,0(8) _litmus_P0_5_: addi 10,10,-1 _litmus_P0_6_: Lit__L1: _litmus_P0_7_: cmpwi 10,0 _litmus_P0_8_: bgt Lit__L0 _litmus_P6_0_: b Lit__L13 _litmus_P6_1_: Lit__L12: _litmus_P6_2_: li 11,1 _litmus_P6_3_: stw 11,0(7) _litmus_P6_4_: lwz 30,0(8) _litmus_P6_5_: addi 10,10,-1 _litmus_P6_6_: Lit__L13: _litmus_P6_7_: cmpwi 10,0 _litmus_P6_8_: bgt Lit__L12 _litmus_P5_0_: b Lit__L11 _litmus_P5_1_: Lit__L10: _litmus_P5_2_: li 11,1 _litmus_P5_3_: stw 11,0(7) _litmus_P5_4_: lwz 30,0(8) _litmus_P5_5_: addi 10,10,-1 _litmus_P5_6_: Lit__L11: _litmus_P5_7_: cmpwi 10,0 _litmus_P5_8_: bgt Lit__L10 _litmus_P4_0_: b Lit__L9 _litmus_P4_1_: Lit__L8: _litmus_P4_2_: li 11,1 _litmus_P4_3_: stw 11,0(7) _litmus_P4_4_: lwz 30,0(8) _litmus_P4_5_: addi 10,10,-1 _litmus_P4_6_: Lit__L9: _litmus_P4_7_: cmpwi 10,0 _litmus_P4_8_: bgt Lit__L8 _litmus_P3_0_: b Lit__L7 _litmus_P3_1_: Lit__L6: _litmus_P3_2_: li 11,1 _litmus_P3_3_: stw 11,0(28) _litmus_P3_4_: lwz 30,0(8) _litmus_P3_5_: addi 10,10,-1 _litmus_P3_6_: Lit__L7: _litmus_P3_7_: cmpwi 10,0 _litmus_P3_8_: bgt Lit__L6 _litmus_P2_0_: b Lit__L5 _litmus_P2_1_: Lit__L4: _litmus_P2_2_: li 11,1 _litmus_P2_3_: stw 11,0(8) _litmus_P2_4_: lwz 30,0(28) _litmus_P2_5_: addi 10,10,-1 _litmus_P2_6_: Lit__L5: _litmus_P2_7_: cmpwi 10,0 _litmus_P2_8_: bgt Lit__L4 Test X07 Allowed Histogram (1 states) 1 :>0:r3=1; 1:r3=1; 2:r3=1; 3:r3=1; 4:r3=1; 5:r3=1; 6:r3=1; No Witnesses Positive: 0, Negative: 1 Condition exists (0:r3=0 /\ 1:r3=0 /\ 2:r3=0 /\ 3:r3=0 /\ 4:r3=0 /\ 5:r3=0 /\ 6:r3=0) is NOT validated Hash=bc93131955d76cdbeefc3f5c3490abc2 Observation X07 Never 0 1 Time X07 0.38 %%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%% % Results for PodWR/X08.litmus % %%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%% PPC X08 "PodWR Fre PodWR Fre PodWR Fre PodWR Fre PodWR Fre PodWR Fre PodWR Fre PodWR Fre" {0:r2=e; 0:r4=x; 1:r2=x; 1:r4=y; 2:r2=y; 2:r4=z; 3:r2=z; 3:r4=a; 4:r2=a; 4:r4=b; 5:r2=b; 5:r4=c; 6:r2=c; 6:r4=d; 7:r2=d; 7:r4=e;} P0 | P1 | P2 | P3 | P4 | P5 | P6 | P7 ; li r1,1 | li r1,1 | li r1,1 | li r1,1 | li r1,1 | li r1,1 | li r1,1 | li r1,1 ; stw r1,0(r2) | stw r1,0(r2) | stw r1,0(r2) | stw r1,0(r2) | stw r1,0(r2) | stw r1,0(r2) | stw r1,0(r2) | stw r1,0(r2) ; lwz r3,0(r4) | lwz r3,0(r4) | lwz r3,0(r4) | lwz r3,0(r4) | lwz r3,0(r4) | lwz r3,0(r4) | lwz r3,0(r4) | lwz r3,0(r4) ; exists (0:r3=0 /\ 1:r3=0 /\ 2:r3=0 /\ 3:r3=0 /\ 4:r3=0 /\ 5:r3=0 /\ 6:r3=0 /\ 7:r3=0) Generated assembler _litmus_P1_0_: b Lit__L3 _litmus_P1_1_: Lit__L2: _litmus_P1_2_: li 11,1 _litmus_P1_3_: stw 11,0(7) _litmus_P1_4_: lwz 31,0(8) _litmus_P1_5_: addi 10,10,-1 _litmus_P1_6_: Lit__L3: _litmus_P1_7_: cmpwi 10,0 _litmus_P1_8_: bgt Lit__L2 _litmus_P0_0_: b Lit__L1 _litmus_P0_1_: Lit__L0: _litmus_P0_2_: li 11,1 _litmus_P0_3_: stw 11,0(7) _litmus_P0_4_: lwz 31,0(8) _litmus_P0_5_: addi 10,10,-1 _litmus_P0_6_: Lit__L1: _litmus_P0_7_: cmpwi 10,0 _litmus_P0_8_: bgt Lit__L0 _litmus_P7_0_: b Lit__L15 _litmus_P7_1_: Lit__L14: _litmus_P7_2_: li 11,1 _litmus_P7_3_: stw 11,0(7) _litmus_P7_4_: lwz 31,0(8) _litmus_P7_5_: addi 10,10,-1 _litmus_P7_6_: Lit__L15: _litmus_P7_7_: cmpwi 10,0 _litmus_P7_8_: bgt Lit__L14 _litmus_P6_0_: b Lit__L13 _litmus_P6_1_: Lit__L12: _litmus_P6_2_: li 11,1 _litmus_P6_3_: stw 11,0(7) _litmus_P6_4_: lwz 31,0(8) _litmus_P6_5_: addi 10,10,-1 _litmus_P6_6_: Lit__L13: _litmus_P6_7_: cmpwi 10,0 _litmus_P6_8_: bgt Lit__L12 _litmus_P5_0_: b Lit__L11 _litmus_P5_1_: Lit__L10: _litmus_P5_2_: li 11,1 _litmus_P5_3_: stw 11,0(7) _litmus_P5_4_: lwz 31,0(8) _litmus_P5_5_: addi 10,10,-1 _litmus_P5_6_: Lit__L11: _litmus_P5_7_: cmpwi 10,0 _litmus_P5_8_: bgt Lit__L10 _litmus_P4_0_: b Lit__L9 _litmus_P4_1_: Lit__L8: _litmus_P4_2_: li 11,1 _litmus_P4_3_: stw 11,0(7) _litmus_P4_4_: lwz 31,0(8) _litmus_P4_5_: addi 10,10,-1 _litmus_P4_6_: Lit__L9: _litmus_P4_7_: cmpwi 10,0 _litmus_P4_8_: bgt Lit__L8 _litmus_P3_0_: b Lit__L7 _litmus_P3_1_: Lit__L6: _litmus_P3_2_: li 11,1 _litmus_P3_3_: stw 11,0(28) _litmus_P3_4_: lwz 31,0(8) _litmus_P3_5_: addi 10,10,-1 _litmus_P3_6_: Lit__L7: _litmus_P3_7_: cmpwi 10,0 _litmus_P3_8_: bgt Lit__L6 _litmus_P2_0_: b Lit__L5 _litmus_P2_1_: Lit__L4: _litmus_P2_2_: li 11,1 _litmus_P2_3_: stw 11,0(8) _litmus_P2_4_: lwz 31,0(28) _litmus_P2_5_: addi 10,10,-1 _litmus_P2_6_: Lit__L5: _litmus_P2_7_: cmpwi 10,0 _litmus_P2_8_: bgt Lit__L4 Test X08 Allowed Histogram (1 states) 1 :>0:r3=1; 1:r3=1; 2:r3=1; 3:r3=1; 4:r3=1; 5:r3=1; 6:r3=1; 7:r3=1; No Witnesses Positive: 0, Negative: 1 Condition exists (0:r3=0 /\ 1:r3=0 /\ 2:r3=0 /\ 3:r3=0 /\ 4:r3=0 /\ 5:r3=0 /\ 6:r3=0 /\ 7:r3=0) is NOT validated Hash=db171753b5c288c65cfe721122e19a2b Observation X08 Never 0 1 Time X08 0.45 %%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%% % Results for PodWR/F01.litmus % %%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%% PPC F01 "reference, one thread" {0:r2=y; 0:r4=x;} P0 ; li r1,1 ; stw r1,0(r2) ; sync ; lwz r3,0(r4) ; locations [0:r3; ] forall (true) Generated assembler _litmus_P0_0_: b Lit__L1 _litmus_P0_1_: Lit__L0: _litmus_P0_2_: li 11,1 _litmus_P0_3_: stw 11,0(28) _litmus_P0_4_: sync _litmus_P0_5_: lwz 31,0(8) _litmus_P0_6_: addi 10,10,-1 _litmus_P0_7_: Lit__L1: _litmus_P0_8_: cmpwi 10,0 _litmus_P0_9_: bgt Lit__L0 Test F01 Required Histogram (1 states) 1 :>0:r3=0; Ok Witnesses Positive: 1, Negative: 0 Condition forall (true) is validated Hash=1ec8232c7aac468376f6113fb17940c5 Observation F01 Always 1 0 Time F01 2.05 %%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%% % Results for PodWR/F02.litmus % %%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%% PPC F02 "PodWR Fre PodWR Fre" {0:r2=y; 0:r4=x; 1:r2=x; 1:r4=y;} P0 | P1 ; li r1,1 | li r1,1 ; stw r1,0(r2) | stw r1,0(r2) ; sync | sync ; lwz r3,0(r4) | lwz r3,0(r4) ; exists (0:r3=0 /\ 1:r3=0) Generated assembler _litmus_P1_0_: b Lit__L3 _litmus_P1_1_: Lit__L2: _litmus_P1_2_: li 11,1 _litmus_P1_3_: stw 11,0(8) _litmus_P1_4_: sync _litmus_P1_5_: lwz 31,0(28) _litmus_P1_6_: addi 10,10,-1 _litmus_P1_7_: Lit__L3: _litmus_P1_8_: cmpwi 10,0 _litmus_P1_9_: bgt Lit__L2 _litmus_P0_0_: b Lit__L1 _litmus_P0_1_: Lit__L0: _litmus_P0_2_: li 11,1 _litmus_P0_3_: stw 11,0(28) _litmus_P0_4_: sync _litmus_P0_5_: lwz 31,0(8) _litmus_P0_6_: addi 10,10,-1 _litmus_P0_7_: Lit__L1: _litmus_P0_8_: cmpwi 10,0 _litmus_P0_9_: bgt Lit__L0 Test F02 Allowed Histogram (1 states) 1 :>0:r3=1; 1:r3=1; No Witnesses Positive: 0, Negative: 1 Condition exists (0:r3=0 /\ 1:r3=0) is NOT validated Hash=a465588c5793d03a277e8d10260275cc Observation F02 Never 0 1 Time F02 8.32 %%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%% % Results for PodWR/F03.litmus % %%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%% PPC F03 "PodWR Fre PodWR Fre PodWR Fre" {0:r2=z; 0:r4=x; 1:r2=x; 1:r4=y; 2:r2=y; 2:r4=z;} P0 | P1 | P2 ; li r1,1 | li r1,1 | li r1,1 ; stw r1,0(r2) | stw r1,0(r2) | stw r1,0(r2) ; sync | sync | sync ; lwz r3,0(r4) | lwz r3,0(r4) | lwz r3,0(r4) ; exists (0:r3=0 /\ 1:r3=0 /\ 2:r3=0) Generated assembler _litmus_P1_0_: b Lit__L3 _litmus_P1_1_: Lit__L2: _litmus_P1_2_: li 11,1 _litmus_P1_3_: stw 11,0(7) _litmus_P1_4_: sync _litmus_P1_5_: lwz 30,0(8) _litmus_P1_6_: addi 10,10,-1 _litmus_P1_7_: Lit__L3: _litmus_P1_8_: cmpwi 10,0 _litmus_P1_9_: bgt Lit__L2 _litmus_P0_0_: b Lit__L1 _litmus_P0_1_: Lit__L0: _litmus_P0_2_: li 11,1 _litmus_P0_3_: stw 11,0(28) _litmus_P0_4_: sync _litmus_P0_5_: lwz 30,0(8) _litmus_P0_6_: addi 10,10,-1 _litmus_P0_7_: Lit__L1: _litmus_P0_8_: cmpwi 10,0 _litmus_P0_9_: bgt Lit__L0 _litmus_P2_0_: b Lit__L5 _litmus_P2_1_: Lit__L4: _litmus_P2_2_: li 11,1 _litmus_P2_3_: stw 11,0(8) _litmus_P2_4_: sync _litmus_P2_5_: lwz 30,0(28) _litmus_P2_6_: addi 10,10,-1 _litmus_P2_7_: Lit__L5: _litmus_P2_8_: cmpwi 10,0 _litmus_P2_9_: bgt Lit__L4 Test F03 Allowed Histogram (1 states) 1 :>0:r3=1; 1:r3=1; 2:r3=1; No Witnesses Positive: 0, Negative: 1 Condition exists (0:r3=0 /\ 1:r3=0 /\ 2:r3=0) is NOT validated Hash=3e0496ec00349e1e6dc68fd1bca7fae5 Observation F03 Never 0 1 Time F03 15.79 %%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%% % Results for PodWR/F04.litmus % %%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%% PPC F04 "PodWR Fre PodWR Fre PodWR Fre PodWR Fre" {0:r2=a; 0:r4=x; 1:r2=x; 1:r4=y; 2:r2=y; 2:r4=z; 3:r2=z; 3:r4=a;} P0 | P1 | P2 | P3 ; li r1,1 | li r1,1 | li r1,1 | li r1,1 ; stw r1,0(r2) | stw r1,0(r2) | stw r1,0(r2) | stw r1,0(r2) ; sync | sync | sync | sync ; lwz r3,0(r4) | lwz r3,0(r4) | lwz r3,0(r4) | lwz r3,0(r4) ; exists (0:r3=0 /\ 1:r3=0 /\ 2:r3=0 /\ 3:r3=0) Generated assembler _litmus_P1_0_: b Lit__L3 _litmus_P1_1_: Lit__L2: _litmus_P1_2_: li 11,1 _litmus_P1_3_: stw 11,0(7) _litmus_P1_4_: sync _litmus_P1_5_: lwz 31,0(8) _litmus_P1_6_: addi 10,10,-1 _litmus_P1_7_: Lit__L3: _litmus_P1_8_: cmpwi 10,0 _litmus_P1_9_: bgt Lit__L2 _litmus_P0_0_: b Lit__L1 _litmus_P0_1_: Lit__L0: _litmus_P0_2_: li 11,1 _litmus_P0_3_: stw 11,0(7) _litmus_P0_4_: sync _litmus_P0_5_: lwz 31,0(8) _litmus_P0_6_: addi 10,10,-1 _litmus_P0_7_: Lit__L1: _litmus_P0_8_: cmpwi 10,0 _litmus_P0_9_: bgt Lit__L0 _litmus_P3_0_: b Lit__L7 _litmus_P3_1_: Lit__L6: _litmus_P3_2_: li 11,1 _litmus_P3_3_: stw 11,0(28) _litmus_P3_4_: sync _litmus_P3_5_: lwz 31,0(8) _litmus_P3_6_: addi 10,10,-1 _litmus_P3_7_: Lit__L7: _litmus_P3_8_: cmpwi 10,0 _litmus_P3_9_: bgt Lit__L6 _litmus_P2_0_: b Lit__L5 _litmus_P2_1_: Lit__L4: _litmus_P2_2_: li 11,1 _litmus_P2_3_: stw 11,0(8) _litmus_P2_4_: sync _litmus_P2_5_: lwz 31,0(28) _litmus_P2_6_: addi 10,10,-1 _litmus_P2_7_: Lit__L5: _litmus_P2_8_: cmpwi 10,0 _litmus_P2_9_: bgt Lit__L4 Test F04 Allowed Histogram (1 states) 1 :>0:r3=1; 1:r3=1; 2:r3=1; 3:r3=1; No Witnesses Positive: 0, Negative: 1 Condition exists (0:r3=0 /\ 1:r3=0 /\ 2:r3=0 /\ 3:r3=0) is NOT validated Hash=88aad1532035015029fd9b8d61727883 Observation F04 Never 0 1 Time F04 27.22 %%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%% % Results for PodWR/F05.litmus % %%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%% PPC F05 "PodWR Fre PodWR Fre PodWR Fre PodWR Fre PodWR Fre" {0:r2=b; 0:r4=x; 1:r2=x; 1:r4=y; 2:r2=y; 2:r4=z; 3:r2=z; 3:r4=a; 4:r2=a; 4:r4=b;} P0 | P1 | P2 | P3 | P4 ; li r1,1 | li r1,1 | li r1,1 | li r1,1 | li r1,1 ; stw r1,0(r2) | stw r1,0(r2) | stw r1,0(r2) | stw r1,0(r2) | stw r1,0(r2) ; sync | sync | sync | sync | sync ; lwz r3,0(r4) | lwz r3,0(r4) | lwz r3,0(r4) | lwz r3,0(r4) | lwz r3,0(r4) ; exists (0:r3=0 /\ 1:r3=0 /\ 2:r3=0 /\ 3:r3=0 /\ 4:r3=0) Generated assembler _litmus_P1_0_: b Lit__L3 _litmus_P1_1_: Lit__L2: _litmus_P1_2_: li 11,1 _litmus_P1_3_: stw 11,0(7) _litmus_P1_4_: sync _litmus_P1_5_: lwz 30,0(8) _litmus_P1_6_: addi 10,10,-1 _litmus_P1_7_: Lit__L3: _litmus_P1_8_: cmpwi 10,0 _litmus_P1_9_: bgt Lit__L2 _litmus_P0_0_: b Lit__L1 _litmus_P0_1_: Lit__L0: _litmus_P0_2_: li 11,1 _litmus_P0_3_: stw 11,0(7) _litmus_P0_4_: sync _litmus_P0_5_: lwz 30,0(8) _litmus_P0_6_: addi 10,10,-1 _litmus_P0_7_: Lit__L1: _litmus_P0_8_: cmpwi 10,0 _litmus_P0_9_: bgt Lit__L0 _litmus_P4_0_: b Lit__L9 _litmus_P4_1_: Lit__L8: _litmus_P4_2_: li 11,1 _litmus_P4_3_: stw 11,0(7) _litmus_P4_4_: sync _litmus_P4_5_: lwz 30,0(8) _litmus_P4_6_: addi 10,10,-1 _litmus_P4_7_: Lit__L9: _litmus_P4_8_: cmpwi 10,0 _litmus_P4_9_: bgt Lit__L8 _litmus_P3_0_: b Lit__L7 _litmus_P3_1_: Lit__L6: _litmus_P3_2_: li 11,1 _litmus_P3_3_: stw 11,0(28) _litmus_P3_4_: sync _litmus_P3_5_: lwz 30,0(8) _litmus_P3_6_: addi 10,10,-1 _litmus_P3_7_: Lit__L7: _litmus_P3_8_: cmpwi 10,0 _litmus_P3_9_: bgt Lit__L6 _litmus_P2_0_: b Lit__L5 _litmus_P2_1_: Lit__L4: _litmus_P2_2_: li 11,1 _litmus_P2_3_: stw 11,0(8) _litmus_P2_4_: sync _litmus_P2_5_: lwz 30,0(28) _litmus_P2_6_: addi 10,10,-1 _litmus_P2_7_: Lit__L5: _litmus_P2_8_: cmpwi 10,0 _litmus_P2_9_: bgt Lit__L4 Test F05 Allowed Histogram (1 states) 1 :>0:r3=1; 1:r3=1; 2:r3=1; 3:r3=1; 4:r3=1; No Witnesses Positive: 0, Negative: 1 Condition exists (0:r3=0 /\ 1:r3=0 /\ 2:r3=0 /\ 3:r3=0 /\ 4:r3=0) is NOT validated Hash=32a9fb7b9639958fd89a2e71758336b8 Observation F05 Never 0 1 Time F05 39.76 %%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%% % Results for PodWR/F06.litmus % %%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%% PPC F06 "PodWR Fre PodWR Fre PodWR Fre PodWR Fre PodWR Fre PodWR Fre" {0:r2=c; 0:r4=x; 1:r2=x; 1:r4=y; 2:r2=y; 2:r4=z; 3:r2=z; 3:r4=a; 4:r2=a; 4:r4=b; 5:r2=b; 5:r4=c;} P0 | P1 | P2 | P3 | P4 | P5 ; li r1,1 | li r1,1 | li r1,1 | li r1,1 | li r1,1 | li r1,1 ; stw r1,0(r2) | stw r1,0(r2) | stw r1,0(r2) | stw r1,0(r2) | stw r1,0(r2) | stw r1,0(r2) ; sync | sync | sync | sync | sync | sync ; lwz r3,0(r4) | lwz r3,0(r4) | lwz r3,0(r4) | lwz r3,0(r4) | lwz r3,0(r4) | lwz r3,0(r4) ; exists (0:r3=0 /\ 1:r3=0 /\ 2:r3=0 /\ 3:r3=0 /\ 4:r3=0 /\ 5:r3=0) Generated assembler _litmus_P1_0_: b Lit__L3 _litmus_P1_1_: Lit__L2: _litmus_P1_2_: li 11,1 _litmus_P1_3_: stw 11,0(7) _litmus_P1_4_: sync _litmus_P1_5_: lwz 30,0(8) _litmus_P1_6_: addi 10,10,-1 _litmus_P1_7_: Lit__L3: _litmus_P1_8_: cmpwi 10,0 _litmus_P1_9_: bgt Lit__L2 _litmus_P0_0_: b Lit__L1 _litmus_P0_1_: Lit__L0: _litmus_P0_2_: li 11,1 _litmus_P0_3_: stw 11,0(7) _litmus_P0_4_: sync _litmus_P0_5_: lwz 30,0(8) _litmus_P0_6_: addi 10,10,-1 _litmus_P0_7_: Lit__L1: _litmus_P0_8_: cmpwi 10,0 _litmus_P0_9_: bgt Lit__L0 _litmus_P5_0_: b Lit__L11 _litmus_P5_1_: Lit__L10: _litmus_P5_2_: li 11,1 _litmus_P5_3_: stw 11,0(7) _litmus_P5_4_: sync _litmus_P5_5_: lwz 30,0(8) _litmus_P5_6_: addi 10,10,-1 _litmus_P5_7_: Lit__L11: _litmus_P5_8_: cmpwi 10,0 _litmus_P5_9_: bgt Lit__L10 _litmus_P4_0_: b Lit__L9 _litmus_P4_1_: Lit__L8: _litmus_P4_2_: li 11,1 _litmus_P4_3_: stw 11,0(7) _litmus_P4_4_: sync _litmus_P4_5_: lwz 30,0(8) _litmus_P4_6_: addi 10,10,-1 _litmus_P4_7_: Lit__L9: _litmus_P4_8_: cmpwi 10,0 _litmus_P4_9_: bgt Lit__L8 _litmus_P3_0_: b Lit__L7 _litmus_P3_1_: Lit__L6: _litmus_P3_2_: li 11,1 _litmus_P3_3_: stw 11,0(28) _litmus_P3_4_: sync _litmus_P3_5_: lwz 30,0(8) _litmus_P3_6_: addi 10,10,-1 _litmus_P3_7_: Lit__L7: _litmus_P3_8_: cmpwi 10,0 _litmus_P3_9_: bgt Lit__L6 _litmus_P2_0_: b Lit__L5 _litmus_P2_1_: Lit__L4: _litmus_P2_2_: li 11,1 _litmus_P2_3_: stw 11,0(8) _litmus_P2_4_: sync _litmus_P2_5_: lwz 30,0(28) _litmus_P2_6_: addi 10,10,-1 _litmus_P2_7_: Lit__L5: _litmus_P2_8_: cmpwi 10,0 _litmus_P2_9_: bgt Lit__L4 Test F06 Allowed Histogram (1 states) 1 :>0:r3=1; 1:r3=1; 2:r3=1; 3:r3=1; 4:r3=1; 5:r3=1; No Witnesses Positive: 0, Negative: 1 Condition exists (0:r3=0 /\ 1:r3=0 /\ 2:r3=0 /\ 3:r3=0 /\ 4:r3=0 /\ 5:r3=0) is NOT validated Hash=b2e998417a52a8f0e42c8ed402b9b8c4 Observation F06 Never 0 1 Time F06 54.46 %%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%% % Results for PodWR/F07.litmus % %%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%% PPC F07 "PodWR Fre PodWR Fre PodWR Fre PodWR Fre PodWR Fre PodWR Fre PodWR Fre" {0:r2=d; 0:r4=x; 1:r2=x; 1:r4=y; 2:r2=y; 2:r4=z; 3:r2=z; 3:r4=a; 4:r2=a; 4:r4=b; 5:r2=b; 5:r4=c; 6:r2=c; 6:r4=d;} P0 | P1 | P2 | P3 | P4 | P5 | P6 ; li r1,1 | li r1,1 | li r1,1 | li r1,1 | li r1,1 | li r1,1 | li r1,1 ; stw r1,0(r2) | stw r1,0(r2) | stw r1,0(r2) | stw r1,0(r2) | stw r1,0(r2) | stw r1,0(r2) | stw r1,0(r2) ; sync | sync | sync | sync | sync | sync | sync ; lwz r3,0(r4) | lwz r3,0(r4) | lwz r3,0(r4) | lwz r3,0(r4) | lwz r3,0(r4) | lwz r3,0(r4) | lwz r3,0(r4) ; exists (0:r3=0 /\ 1:r3=0 /\ 2:r3=0 /\ 3:r3=0 /\ 4:r3=0 /\ 5:r3=0 /\ 6:r3=0) Generated assembler _litmus_P1_0_: b Lit__L3 _litmus_P1_1_: Lit__L2: _litmus_P1_2_: li 11,1 _litmus_P1_3_: stw 11,0(7) _litmus_P1_4_: sync _litmus_P1_5_: lwz 30,0(8) _litmus_P1_6_: addi 10,10,-1 _litmus_P1_7_: Lit__L3: _litmus_P1_8_: cmpwi 10,0 _litmus_P1_9_: bgt Lit__L2 _litmus_P0_0_: b Lit__L1 _litmus_P0_1_: Lit__L0: _litmus_P0_2_: li 11,1 _litmus_P0_3_: stw 11,0(7) _litmus_P0_4_: sync _litmus_P0_5_: lwz 30,0(8) _litmus_P0_6_: addi 10,10,-1 _litmus_P0_7_: Lit__L1: _litmus_P0_8_: cmpwi 10,0 _litmus_P0_9_: bgt Lit__L0 _litmus_P6_0_: b Lit__L13 _litmus_P6_1_: Lit__L12: _litmus_P6_2_: li 11,1 _litmus_P6_3_: stw 11,0(7) _litmus_P6_4_: sync _litmus_P6_5_: lwz 30,0(8) _litmus_P6_6_: addi 10,10,-1 _litmus_P6_7_: Lit__L13: _litmus_P6_8_: cmpwi 10,0 _litmus_P6_9_: bgt Lit__L12 _litmus_P5_0_: b Lit__L11 _litmus_P5_1_: Lit__L10: _litmus_P5_2_: li 11,1 _litmus_P5_3_: stw 11,0(7) _litmus_P5_4_: sync _litmus_P5_5_: lwz 30,0(8) _litmus_P5_6_: addi 10,10,-1 _litmus_P5_7_: Lit__L11: _litmus_P5_8_: cmpwi 10,0 _litmus_P5_9_: bgt Lit__L10 _litmus_P4_0_: b Lit__L9 _litmus_P4_1_: Lit__L8: _litmus_P4_2_: li 11,1 _litmus_P4_3_: stw 11,0(7) _litmus_P4_4_: sync _litmus_P4_5_: lwz 30,0(8) _litmus_P4_6_: addi 10,10,-1 _litmus_P4_7_: Lit__L9: _litmus_P4_8_: cmpwi 10,0 _litmus_P4_9_: bgt Lit__L8 _litmus_P3_0_: b Lit__L7 _litmus_P3_1_: Lit__L6: _litmus_P3_2_: li 11,1 _litmus_P3_3_: stw 11,0(28) _litmus_P3_4_: sync _litmus_P3_5_: lwz 30,0(8) _litmus_P3_6_: addi 10,10,-1 _litmus_P3_7_: Lit__L7: _litmus_P3_8_: cmpwi 10,0 _litmus_P3_9_: bgt Lit__L6 _litmus_P2_0_: b Lit__L5 _litmus_P2_1_: Lit__L4: _litmus_P2_2_: li 11,1 _litmus_P2_3_: stw 11,0(8) _litmus_P2_4_: sync _litmus_P2_5_: lwz 30,0(28) _litmus_P2_6_: addi 10,10,-1 _litmus_P2_7_: Lit__L5: _litmus_P2_8_: cmpwi 10,0 _litmus_P2_9_: bgt Lit__L4 Test F07 Allowed Histogram (1 states) 1 :>0:r3=1; 1:r3=1; 2:r3=1; 3:r3=1; 4:r3=1; 5:r3=1; 6:r3=1; No Witnesses Positive: 0, Negative: 1 Condition exists (0:r3=0 /\ 1:r3=0 /\ 2:r3=0 /\ 3:r3=0 /\ 4:r3=0 /\ 5:r3=0 /\ 6:r3=0) is NOT validated Hash=309301f5a87cdbe013395c68728030b0 Observation F07 Never 0 1 Time F07 67.81 %%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%% % Results for PodWR/F08.litmus % %%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%% PPC F08 "PodWR Fre PodWR Fre PodWR Fre PodWR Fre PodWR Fre PodWR Fre PodWR Fre PodWR Fre" {0:r2=e; 0:r4=x; 1:r2=x; 1:r4=y; 2:r2=y; 2:r4=z; 3:r2=z; 3:r4=a; 4:r2=a; 4:r4=b; 5:r2=b; 5:r4=c; 6:r2=c; 6:r4=d; 7:r2=d; 7:r4=e;} P0 | P1 | P2 | P3 | P4 | P5 | P6 | P7 ; li r1,1 | li r1,1 | li r1,1 | li r1,1 | li r1,1 | li r1,1 | li r1,1 | li r1,1 ; stw r1,0(r2) | stw r1,0(r2) | stw r1,0(r2) | stw r1,0(r2) | stw r1,0(r2) | stw r1,0(r2) | stw r1,0(r2) | stw r1,0(r2) ; sync | sync | sync | sync | sync | sync | sync | sync ; lwz r3,0(r4) | lwz r3,0(r4) | lwz r3,0(r4) | lwz r3,0(r4) | lwz r3,0(r4) | lwz r3,0(r4) | lwz r3,0(r4) | lwz r3,0(r4) ; exists (0:r3=0 /\ 1:r3=0 /\ 2:r3=0 /\ 3:r3=0 /\ 4:r3=0 /\ 5:r3=0 /\ 6:r3=0 /\ 7:r3=0) Generated assembler _litmus_P1_0_: b Lit__L3 _litmus_P1_1_: Lit__L2: _litmus_P1_2_: li 11,1 _litmus_P1_3_: stw 11,0(7) _litmus_P1_4_: sync _litmus_P1_5_: lwz 31,0(8) _litmus_P1_6_: addi 10,10,-1 _litmus_P1_7_: Lit__L3: _litmus_P1_8_: cmpwi 10,0 _litmus_P1_9_: bgt Lit__L2 _litmus_P0_0_: b Lit__L1 _litmus_P0_1_: Lit__L0: _litmus_P0_2_: li 11,1 _litmus_P0_3_: stw 11,0(7) _litmus_P0_4_: sync _litmus_P0_5_: lwz 31,0(8) _litmus_P0_6_: addi 10,10,-1 _litmus_P0_7_: Lit__L1: _litmus_P0_8_: cmpwi 10,0 _litmus_P0_9_: bgt Lit__L0 _litmus_P7_0_: b Lit__L15 _litmus_P7_1_: Lit__L14: _litmus_P7_2_: li 11,1 _litmus_P7_3_: stw 11,0(7) _litmus_P7_4_: sync _litmus_P7_5_: lwz 31,0(8) _litmus_P7_6_: addi 10,10,-1 _litmus_P7_7_: Lit__L15: _litmus_P7_8_: cmpwi 10,0 _litmus_P7_9_: bgt Lit__L14 _litmus_P6_0_: b Lit__L13 _litmus_P6_1_: Lit__L12: _litmus_P6_2_: li 11,1 _litmus_P6_3_: stw 11,0(7) _litmus_P6_4_: sync _litmus_P6_5_: lwz 31,0(8) _litmus_P6_6_: addi 10,10,-1 _litmus_P6_7_: Lit__L13: _litmus_P6_8_: cmpwi 10,0 _litmus_P6_9_: bgt Lit__L12 _litmus_P5_0_: b Lit__L11 _litmus_P5_1_: Lit__L10: _litmus_P5_2_: li 11,1 _litmus_P5_3_: stw 11,0(7) _litmus_P5_4_: sync _litmus_P5_5_: lwz 31,0(8) _litmus_P5_6_: addi 10,10,-1 _litmus_P5_7_: Lit__L11: _litmus_P5_8_: cmpwi 10,0 _litmus_P5_9_: bgt Lit__L10 _litmus_P4_0_: b Lit__L9 _litmus_P4_1_: Lit__L8: _litmus_P4_2_: li 11,1 _litmus_P4_3_: stw 11,0(7) _litmus_P4_4_: sync _litmus_P4_5_: lwz 31,0(8) _litmus_P4_6_: addi 10,10,-1 _litmus_P4_7_: Lit__L9: _litmus_P4_8_: cmpwi 10,0 _litmus_P4_9_: bgt Lit__L8 _litmus_P3_0_: b Lit__L7 _litmus_P3_1_: Lit__L6: _litmus_P3_2_: li 11,1 _litmus_P3_3_: stw 11,0(28) _litmus_P3_4_: sync _litmus_P3_5_: lwz 31,0(8) _litmus_P3_6_: addi 10,10,-1 _litmus_P3_7_: Lit__L7: _litmus_P3_8_: cmpwi 10,0 _litmus_P3_9_: bgt Lit__L6 _litmus_P2_0_: b Lit__L5 _litmus_P2_1_: Lit__L4: _litmus_P2_2_: li 11,1 _litmus_P2_3_: stw 11,0(8) _litmus_P2_4_: sync _litmus_P2_5_: lwz 31,0(28) _litmus_P2_6_: addi 10,10,-1 _litmus_P2_7_: Lit__L5: _litmus_P2_8_: cmpwi 10,0 _litmus_P2_9_: bgt Lit__L4 Test F08 Allowed Histogram (1 states) 1 :>0:r3=1; 1:r3=1; 2:r3=1; 3:r3=1; 4:r3=1; 5:r3=1; 6:r3=1; 7:r3=1; No Witnesses Positive: 0, Negative: 1 Condition exists (0:r3=0 /\ 1:r3=0 /\ 2:r3=0 /\ 3:r3=0 /\ 4:r3=0 /\ 5:r3=0 /\ 6:r3=0 /\ 7:r3=0) is NOT validated Hash=6bb8aed0278838c9d4dba3115901ac60 Observation F08 Never 0 1 Time F08 64.42 %%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%% % Results for PodWR/W01.litmus % %%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%% PPC W01 "reference, one thread" {0:r2=y; 0:r4=x;} P0 ; li r1,1 ; stw r1,0(r2) ; lwsync ; lwz r3,0(r4) ; locations [0:r3; ] forall (true) Generated assembler _litmus_P0_0_: b Lit__L1 _litmus_P0_1_: Lit__L0: _litmus_P0_2_: li 11,1 _litmus_P0_3_: stw 11,0(28) _litmus_P0_4_: lwsync _litmus_P0_5_: lwz 31,0(8) _litmus_P0_6_: addi 10,10,-1 _litmus_P0_7_: Lit__L1: _litmus_P0_8_: cmpwi 10,0 _litmus_P0_9_: bgt Lit__L0 Test W01 Required Histogram (1 states) 1 :>0:r3=0; Ok Witnesses Positive: 1, Negative: 0 Condition forall (true) is validated Hash=9300a90aacc71b0bb839b6ff80530fcc Observation W01 Always 1 0 Time W01 0.80 %%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%% % Results for PodWR/W02.litmus % %%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%% PPC W02 "PodWR Wre PodWR Wre" {0:r2=y; 0:r4=x; 1:r2=x; 1:r4=y;} P0 | P1 ; li r1,1 | li r1,1 ; stw r1,0(r2) | stw r1,0(r2) ; lwsync | lwsync ; lwz r3,0(r4) | lwz r3,0(r4) ; exists (0:r3=0 /\ 1:r3=0) Generated assembler _litmus_P1_0_: b Lit__L3 _litmus_P1_1_: Lit__L2: _litmus_P1_2_: li 11,1 _litmus_P1_3_: stw 11,0(8) _litmus_P1_4_: lwsync _litmus_P1_5_: lwz 31,0(28) _litmus_P1_6_: addi 10,10,-1 _litmus_P1_7_: Lit__L3: _litmus_P1_8_: cmpwi 10,0 _litmus_P1_9_: bgt Lit__L2 _litmus_P0_0_: b Lit__L1 _litmus_P0_1_: Lit__L0: _litmus_P0_2_: li 11,1 _litmus_P0_3_: stw 11,0(28) _litmus_P0_4_: lwsync _litmus_P0_5_: lwz 31,0(8) _litmus_P0_6_: addi 10,10,-1 _litmus_P0_7_: Lit__L1: _litmus_P0_8_: cmpwi 10,0 _litmus_P0_9_: bgt Lit__L0 Test W02 Allowed Histogram (1 states) 1 :>0:r3=1; 1:r3=1; No Witnesses Positive: 0, Negative: 1 Condition exists (0:r3=0 /\ 1:r3=0) is NOT validated Hash=86ac3ae456ddd94ba97a98bdc65ce7a1 Observation W02 Never 0 1 Time W02 3.30 %%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%% % Results for PodWR/W03.litmus % %%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%% PPC W03 "PodWR Wre PodWR Wre PodWR Wre" {0:r2=z; 0:r4=x; 1:r2=x; 1:r4=y; 2:r2=y; 2:r4=z;} P0 | P1 | P2 ; li r1,1 | li r1,1 | li r1,1 ; stw r1,0(r2) | stw r1,0(r2) | stw r1,0(r2) ; lwsync | lwsync | lwsync ; lwz r3,0(r4) | lwz r3,0(r4) | lwz r3,0(r4) ; exists (0:r3=0 /\ 1:r3=0 /\ 2:r3=0) Generated assembler _litmus_P1_0_: b Lit__L3 _litmus_P1_1_: Lit__L2: _litmus_P1_2_: li 11,1 _litmus_P1_3_: stw 11,0(7) _litmus_P1_4_: lwsync _litmus_P1_5_: lwz 30,0(8) _litmus_P1_6_: addi 10,10,-1 _litmus_P1_7_: Lit__L3: _litmus_P1_8_: cmpwi 10,0 _litmus_P1_9_: bgt Lit__L2 _litmus_P0_0_: b Lit__L1 _litmus_P0_1_: Lit__L0: _litmus_P0_2_: li 11,1 _litmus_P0_3_: stw 11,0(28) _litmus_P0_4_: lwsync _litmus_P0_5_: lwz 30,0(8) _litmus_P0_6_: addi 10,10,-1 _litmus_P0_7_: Lit__L1: _litmus_P0_8_: cmpwi 10,0 _litmus_P0_9_: bgt Lit__L0 _litmus_P2_0_: b Lit__L5 _litmus_P2_1_: Lit__L4: _litmus_P2_2_: li 11,1 _litmus_P2_3_: stw 11,0(8) _litmus_P2_4_: lwsync _litmus_P2_5_: lwz 30,0(28) _litmus_P2_6_: addi 10,10,-1 _litmus_P2_7_: Lit__L5: _litmus_P2_8_: cmpwi 10,0 _litmus_P2_9_: bgt Lit__L4 Test W03 Allowed Histogram (1 states) 1 :>0:r3=1; 1:r3=1; 2:r3=1; No Witnesses Positive: 0, Negative: 1 Condition exists (0:r3=0 /\ 1:r3=0 /\ 2:r3=0) is NOT validated Hash=6f76d616d3ca67d09112adbfa3c06ab3 Observation W03 Never 0 1 Time W03 7.37 %%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%% % Results for PodWR/W04.litmus % %%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%% PPC W04 "PodWR Wre PodWR Wre PodWR Wre PodWR Wre" {0:r2=a; 0:r4=x; 1:r2=x; 1:r4=y; 2:r2=y; 2:r4=z; 3:r2=z; 3:r4=a;} P0 | P1 | P2 | P3 ; li r1,1 | li r1,1 | li r1,1 | li r1,1 ; stw r1,0(r2) | stw r1,0(r2) | stw r1,0(r2) | stw r1,0(r2) ; lwsync | lwsync | lwsync | lwsync ; lwz r3,0(r4) | lwz r3,0(r4) | lwz r3,0(r4) | lwz r3,0(r4) ; exists (0:r3=0 /\ 1:r3=0 /\ 2:r3=0 /\ 3:r3=0) Generated assembler _litmus_P1_0_: b Lit__L3 _litmus_P1_1_: Lit__L2: _litmus_P1_2_: li 11,1 _litmus_P1_3_: stw 11,0(7) _litmus_P1_4_: lwsync _litmus_P1_5_: lwz 31,0(8) _litmus_P1_6_: addi 10,10,-1 _litmus_P1_7_: Lit__L3: _litmus_P1_8_: cmpwi 10,0 _litmus_P1_9_: bgt Lit__L2 _litmus_P0_0_: b Lit__L1 _litmus_P0_1_: Lit__L0: _litmus_P0_2_: li 11,1 _litmus_P0_3_: stw 11,0(7) _litmus_P0_4_: lwsync _litmus_P0_5_: lwz 31,0(8) _litmus_P0_6_: addi 10,10,-1 _litmus_P0_7_: Lit__L1: _litmus_P0_8_: cmpwi 10,0 _litmus_P0_9_: bgt Lit__L0 _litmus_P3_0_: b Lit__L7 _litmus_P3_1_: Lit__L6: _litmus_P3_2_: li 11,1 _litmus_P3_3_: stw 11,0(28) _litmus_P3_4_: lwsync _litmus_P3_5_: lwz 31,0(8) _litmus_P3_6_: addi 10,10,-1 _litmus_P3_7_: Lit__L7: _litmus_P3_8_: cmpwi 10,0 _litmus_P3_9_: bgt Lit__L6 _litmus_P2_0_: b Lit__L5 _litmus_P2_1_: Lit__L4: _litmus_P2_2_: li 11,1 _litmus_P2_3_: stw 11,0(8) _litmus_P2_4_: lwsync _litmus_P2_5_: lwz 31,0(28) _litmus_P2_6_: addi 10,10,-1 _litmus_P2_7_: Lit__L5: _litmus_P2_8_: cmpwi 10,0 _litmus_P2_9_: bgt Lit__L4 Test W04 Allowed Histogram (1 states) 1 :>0:r3=1; 1:r3=1; 2:r3=1; 3:r3=1; No Witnesses Positive: 0, Negative: 1 Condition exists (0:r3=0 /\ 1:r3=0 /\ 2:r3=0 /\ 3:r3=0) is NOT validated Hash=98a8c8ac09ac79008668ec1dc1d7342f Observation W04 Never 0 1 Time W04 14.14 %%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%% % Results for PodWR/W05.litmus % %%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%% PPC W05 "PodWR Wre PodWR Wre PodWR Wre PodWR Wre PodWR Wre" {0:r2=b; 0:r4=x; 1:r2=x; 1:r4=y; 2:r2=y; 2:r4=z; 3:r2=z; 3:r4=a; 4:r2=a; 4:r4=b;} P0 | P1 | P2 | P3 | P4 ; li r1,1 | li r1,1 | li r1,1 | li r1,1 | li r1,1 ; stw r1,0(r2) | stw r1,0(r2) | stw r1,0(r2) | stw r1,0(r2) | stw r1,0(r2) ; lwsync | lwsync | lwsync | lwsync | lwsync ; lwz r3,0(r4) | lwz r3,0(r4) | lwz r3,0(r4) | lwz r3,0(r4) | lwz r3,0(r4) ; exists (0:r3=0 /\ 1:r3=0 /\ 2:r3=0 /\ 3:r3=0 /\ 4:r3=0) Generated assembler _litmus_P1_0_: b Lit__L3 _litmus_P1_1_: Lit__L2: _litmus_P1_2_: li 11,1 _litmus_P1_3_: stw 11,0(7) _litmus_P1_4_: lwsync _litmus_P1_5_: lwz 30,0(8) _litmus_P1_6_: addi 10,10,-1 _litmus_P1_7_: Lit__L3: _litmus_P1_8_: cmpwi 10,0 _litmus_P1_9_: bgt Lit__L2 _litmus_P0_0_: b Lit__L1 _litmus_P0_1_: Lit__L0: _litmus_P0_2_: li 11,1 _litmus_P0_3_: stw 11,0(7) _litmus_P0_4_: lwsync _litmus_P0_5_: lwz 30,0(8) _litmus_P0_6_: addi 10,10,-1 _litmus_P0_7_: Lit__L1: _litmus_P0_8_: cmpwi 10,0 _litmus_P0_9_: bgt Lit__L0 _litmus_P4_0_: b Lit__L9 _litmus_P4_1_: Lit__L8: _litmus_P4_2_: li 11,1 _litmus_P4_3_: stw 11,0(7) _litmus_P4_4_: lwsync _litmus_P4_5_: lwz 30,0(8) _litmus_P4_6_: addi 10,10,-1 _litmus_P4_7_: Lit__L9: _litmus_P4_8_: cmpwi 10,0 _litmus_P4_9_: bgt Lit__L8 _litmus_P3_0_: b Lit__L7 _litmus_P3_1_: Lit__L6: _litmus_P3_2_: li 11,1 _litmus_P3_3_: stw 11,0(28) _litmus_P3_4_: lwsync _litmus_P3_5_: lwz 30,0(8) _litmus_P3_6_: addi 10,10,-1 _litmus_P3_7_: Lit__L7: _litmus_P3_8_: cmpwi 10,0 _litmus_P3_9_: bgt Lit__L6 _litmus_P2_0_: b Lit__L5 _litmus_P2_1_: Lit__L4: _litmus_P2_2_: li 11,1 _litmus_P2_3_: stw 11,0(8) _litmus_P2_4_: lwsync _litmus_P2_5_: lwz 30,0(28) _litmus_P2_6_: addi 10,10,-1 _litmus_P2_7_: Lit__L5: _litmus_P2_8_: cmpwi 10,0 _litmus_P2_9_: bgt Lit__L4 Test W05 Allowed Histogram (1 states) 1 :>0:r3=1; 1:r3=1; 2:r3=1; 3:r3=1; 4:r3=1; No Witnesses Positive: 0, Negative: 1 Condition exists (0:r3=0 /\ 1:r3=0 /\ 2:r3=0 /\ 3:r3=0 /\ 4:r3=0) is NOT validated Hash=2966a42973e6599fd007ed52a2c39139 Observation W05 Never 0 1 Time W05 22.37 %%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%% % Results for PodWR/W06.litmus % %%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%% PPC W06 "PodWR Wre PodWR Wre PodWR Wre PodWR Wre PodWR Wre PodWR Wre" {0:r2=c; 0:r4=x; 1:r2=x; 1:r4=y; 2:r2=y; 2:r4=z; 3:r2=z; 3:r4=a; 4:r2=a; 4:r4=b; 5:r2=b; 5:r4=c;} P0 | P1 | P2 | P3 | P4 | P5 ; li r1,1 | li r1,1 | li r1,1 | li r1,1 | li r1,1 | li r1,1 ; stw r1,0(r2) | stw r1,0(r2) | stw r1,0(r2) | stw r1,0(r2) | stw r1,0(r2) | stw r1,0(r2) ; lwsync | lwsync | lwsync | lwsync | lwsync | lwsync ; lwz r3,0(r4) | lwz r3,0(r4) | lwz r3,0(r4) | lwz r3,0(r4) | lwz r3,0(r4) | lwz r3,0(r4) ; exists (0:r3=0 /\ 1:r3=0 /\ 2:r3=0 /\ 3:r3=0 /\ 4:r3=0 /\ 5:r3=0) Generated assembler _litmus_P1_0_: b Lit__L3 _litmus_P1_1_: Lit__L2: _litmus_P1_2_: li 11,1 _litmus_P1_3_: stw 11,0(7) _litmus_P1_4_: lwsync _litmus_P1_5_: lwz 30,0(8) _litmus_P1_6_: addi 10,10,-1 _litmus_P1_7_: Lit__L3: _litmus_P1_8_: cmpwi 10,0 _litmus_P1_9_: bgt Lit__L2 _litmus_P0_0_: b Lit__L1 _litmus_P0_1_: Lit__L0: _litmus_P0_2_: li 11,1 _litmus_P0_3_: stw 11,0(7) _litmus_P0_4_: lwsync _litmus_P0_5_: lwz 30,0(8) _litmus_P0_6_: addi 10,10,-1 _litmus_P0_7_: Lit__L1: _litmus_P0_8_: cmpwi 10,0 _litmus_P0_9_: bgt Lit__L0 _litmus_P5_0_: b Lit__L11 _litmus_P5_1_: Lit__L10: _litmus_P5_2_: li 11,1 _litmus_P5_3_: stw 11,0(7) _litmus_P5_4_: lwsync _litmus_P5_5_: lwz 30,0(8) _litmus_P5_6_: addi 10,10,-1 _litmus_P5_7_: Lit__L11: _litmus_P5_8_: cmpwi 10,0 _litmus_P5_9_: bgt Lit__L10 _litmus_P4_0_: b Lit__L9 _litmus_P4_1_: Lit__L8: _litmus_P4_2_: li 11,1 _litmus_P4_3_: stw 11,0(7) _litmus_P4_4_: lwsync _litmus_P4_5_: lwz 30,0(8) _litmus_P4_6_: addi 10,10,-1 _litmus_P4_7_: Lit__L9: _litmus_P4_8_: cmpwi 10,0 _litmus_P4_9_: bgt Lit__L8 _litmus_P3_0_: b Lit__L7 _litmus_P3_1_: Lit__L6: _litmus_P3_2_: li 11,1 _litmus_P3_3_: stw 11,0(28) _litmus_P3_4_: lwsync _litmus_P3_5_: lwz 30,0(8) _litmus_P3_6_: addi 10,10,-1 _litmus_P3_7_: Lit__L7: _litmus_P3_8_: cmpwi 10,0 _litmus_P3_9_: bgt Lit__L6 _litmus_P2_0_: b Lit__L5 _litmus_P2_1_: Lit__L4: _litmus_P2_2_: li 11,1 _litmus_P2_3_: stw 11,0(8) _litmus_P2_4_: lwsync _litmus_P2_5_: lwz 30,0(28) _litmus_P2_6_: addi 10,10,-1 _litmus_P2_7_: Lit__L5: _litmus_P2_8_: cmpwi 10,0 _litmus_P2_9_: bgt Lit__L4 Test W06 Allowed Histogram (1 states) 1 :>0:r3=1; 1:r3=1; 2:r3=1; 3:r3=1; 4:r3=1; 5:r3=1; No Witnesses Positive: 0, Negative: 1 Condition exists (0:r3=0 /\ 1:r3=0 /\ 2:r3=0 /\ 3:r3=0 /\ 4:r3=0 /\ 5:r3=0) is NOT validated Hash=1c906a5c231fd9b4bf418a80f61b0c52 Observation W06 Never 0 1 Time W06 30.34 %%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%% % Results for PodWR/W07.litmus % %%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%% PPC W07 "PodWR Wre PodWR Wre PodWR Wre PodWR Wre PodWR Wre PodWR Wre PodWR Wre" {0:r2=d; 0:r4=x; 1:r2=x; 1:r4=y; 2:r2=y; 2:r4=z; 3:r2=z; 3:r4=a; 4:r2=a; 4:r4=b; 5:r2=b; 5:r4=c; 6:r2=c; 6:r4=d;} P0 | P1 | P2 | P3 | P4 | P5 | P6 ; li r1,1 | li r1,1 | li r1,1 | li r1,1 | li r1,1 | li r1,1 | li r1,1 ; stw r1,0(r2) | stw r1,0(r2) | stw r1,0(r2) | stw r1,0(r2) | stw r1,0(r2) | stw r1,0(r2) | stw r1,0(r2) ; lwsync | lwsync | lwsync | lwsync | lwsync | lwsync | lwsync ; lwz r3,0(r4) | lwz r3,0(r4) | lwz r3,0(r4) | lwz r3,0(r4) | lwz r3,0(r4) | lwz r3,0(r4) | lwz r3,0(r4) ; exists (0:r3=0 /\ 1:r3=0 /\ 2:r3=0 /\ 3:r3=0 /\ 4:r3=0 /\ 5:r3=0 /\ 6:r3=0) Generated assembler _litmus_P1_0_: b Lit__L3 _litmus_P1_1_: Lit__L2: _litmus_P1_2_: li 11,1 _litmus_P1_3_: stw 11,0(7) _litmus_P1_4_: lwsync _litmus_P1_5_: lwz 30,0(8) _litmus_P1_6_: addi 10,10,-1 _litmus_P1_7_: Lit__L3: _litmus_P1_8_: cmpwi 10,0 _litmus_P1_9_: bgt Lit__L2 _litmus_P0_0_: b Lit__L1 _litmus_P0_1_: Lit__L0: _litmus_P0_2_: li 11,1 _litmus_P0_3_: stw 11,0(7) _litmus_P0_4_: lwsync _litmus_P0_5_: lwz 30,0(8) _litmus_P0_6_: addi 10,10,-1 _litmus_P0_7_: Lit__L1: _litmus_P0_8_: cmpwi 10,0 _litmus_P0_9_: bgt Lit__L0 _litmus_P6_0_: b Lit__L13 _litmus_P6_1_: Lit__L12: _litmus_P6_2_: li 11,1 _litmus_P6_3_: stw 11,0(7) _litmus_P6_4_: lwsync _litmus_P6_5_: lwz 30,0(8) _litmus_P6_6_: addi 10,10,-1 _litmus_P6_7_: Lit__L13: _litmus_P6_8_: cmpwi 10,0 _litmus_P6_9_: bgt Lit__L12 _litmus_P5_0_: b Lit__L11 _litmus_P5_1_: Lit__L10: _litmus_P5_2_: li 11,1 _litmus_P5_3_: stw 11,0(7) _litmus_P5_4_: lwsync _litmus_P5_5_: lwz 30,0(8) _litmus_P5_6_: addi 10,10,-1 _litmus_P5_7_: Lit__L11: _litmus_P5_8_: cmpwi 10,0 _litmus_P5_9_: bgt Lit__L10 _litmus_P4_0_: b Lit__L9 _litmus_P4_1_: Lit__L8: _litmus_P4_2_: li 11,1 _litmus_P4_3_: stw 11,0(7) _litmus_P4_4_: lwsync _litmus_P4_5_: lwz 30,0(8) _litmus_P4_6_: addi 10,10,-1 _litmus_P4_7_: Lit__L9: _litmus_P4_8_: cmpwi 10,0 _litmus_P4_9_: bgt Lit__L8 _litmus_P3_0_: b Lit__L7 _litmus_P3_1_: Lit__L6: _litmus_P3_2_: li 11,1 _litmus_P3_3_: stw 11,0(28) _litmus_P3_4_: lwsync _litmus_P3_5_: lwz 30,0(8) _litmus_P3_6_: addi 10,10,-1 _litmus_P3_7_: Lit__L7: _litmus_P3_8_: cmpwi 10,0 _litmus_P3_9_: bgt Lit__L6 _litmus_P2_0_: b Lit__L5 _litmus_P2_1_: Lit__L4: _litmus_P2_2_: li 11,1 _litmus_P2_3_: stw 11,0(8) _litmus_P2_4_: lwsync _litmus_P2_5_: lwz 30,0(28) _litmus_P2_6_: addi 10,10,-1 _litmus_P2_7_: Lit__L5: _litmus_P2_8_: cmpwi 10,0 _litmus_P2_9_: bgt Lit__L4 Test W07 Allowed Histogram (1 states) 1 :>0:r3=1; 1:r3=1; 2:r3=1; 3:r3=1; 4:r3=1; 5:r3=1; 6:r3=1; No Witnesses Positive: 0, Negative: 1 Condition exists (0:r3=0 /\ 1:r3=0 /\ 2:r3=0 /\ 3:r3=0 /\ 4:r3=0 /\ 5:r3=0 /\ 6:r3=0) is NOT validated Hash=4fa98effade35d6ad81647bdf74f0911 Observation W07 Never 0 1 Time W07 31.02 %%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%% % Results for PodWR/W08.litmus % %%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%% PPC W08 "PodWR Wre PodWR Wre PodWR Wre PodWR Wre PodWR Wre PodWR Wre PodWR Wre PodWR Wre" {0:r2=e; 0:r4=x; 1:r2=x; 1:r4=y; 2:r2=y; 2:r4=z; 3:r2=z; 3:r4=a; 4:r2=a; 4:r4=b; 5:r2=b; 5:r4=c; 6:r2=c; 6:r4=d; 7:r2=d; 7:r4=e;} P0 | P1 | P2 | P3 | P4 | P5 | P6 | P7 ; li r1,1 | li r1,1 | li r1,1 | li r1,1 | li r1,1 | li r1,1 | li r1,1 | li r1,1 ; stw r1,0(r2) | stw r1,0(r2) | stw r1,0(r2) | stw r1,0(r2) | stw r1,0(r2) | stw r1,0(r2) | stw r1,0(r2) | stw r1,0(r2) ; lwsync | lwsync | lwsync | lwsync | lwsync | lwsync | lwsync | lwsync ; lwz r3,0(r4) | lwz r3,0(r4) | lwz r3,0(r4) | lwz r3,0(r4) | lwz r3,0(r4) | lwz r3,0(r4) | lwz r3,0(r4) | lwz r3,0(r4) ; exists (0:r3=0 /\ 1:r3=0 /\ 2:r3=0 /\ 3:r3=0 /\ 4:r3=0 /\ 5:r3=0 /\ 6:r3=0 /\ 7:r3=0) Generated assembler _litmus_P1_0_: b Lit__L3 _litmus_P1_1_: Lit__L2: _litmus_P1_2_: li 11,1 _litmus_P1_3_: stw 11,0(7) _litmus_P1_4_: lwsync _litmus_P1_5_: lwz 31,0(8) _litmus_P1_6_: addi 10,10,-1 _litmus_P1_7_: Lit__L3: _litmus_P1_8_: cmpwi 10,0 _litmus_P1_9_: bgt Lit__L2 _litmus_P0_0_: b Lit__L1 _litmus_P0_1_: Lit__L0: _litmus_P0_2_: li 11,1 _litmus_P0_3_: stw 11,0(7) _litmus_P0_4_: lwsync _litmus_P0_5_: lwz 31,0(8) _litmus_P0_6_: addi 10,10,-1 _litmus_P0_7_: Lit__L1: _litmus_P0_8_: cmpwi 10,0 _litmus_P0_9_: bgt Lit__L0 _litmus_P7_0_: b Lit__L15 _litmus_P7_1_: Lit__L14: _litmus_P7_2_: li 11,1 _litmus_P7_3_: stw 11,0(7) _litmus_P7_4_: lwsync _litmus_P7_5_: lwz 31,0(8) _litmus_P7_6_: addi 10,10,-1 _litmus_P7_7_: Lit__L15: _litmus_P7_8_: cmpwi 10,0 _litmus_P7_9_: bgt Lit__L14 _litmus_P6_0_: b Lit__L13 _litmus_P6_1_: Lit__L12: _litmus_P6_2_: li 11,1 _litmus_P6_3_: stw 11,0(7) _litmus_P6_4_: lwsync _litmus_P6_5_: lwz 31,0(8) _litmus_P6_6_: addi 10,10,-1 _litmus_P6_7_: Lit__L13: _litmus_P6_8_: cmpwi 10,0 _litmus_P6_9_: bgt Lit__L12 _litmus_P5_0_: b Lit__L11 _litmus_P5_1_: Lit__L10: _litmus_P5_2_: li 11,1 _litmus_P5_3_: stw 11,0(7) _litmus_P5_4_: lwsync _litmus_P5_5_: lwz 31,0(8) _litmus_P5_6_: addi 10,10,-1 _litmus_P5_7_: Lit__L11: _litmus_P5_8_: cmpwi 10,0 _litmus_P5_9_: bgt Lit__L10 _litmus_P4_0_: b Lit__L9 _litmus_P4_1_: Lit__L8: _litmus_P4_2_: li 11,1 _litmus_P4_3_: stw 11,0(7) _litmus_P4_4_: lwsync _litmus_P4_5_: lwz 31,0(8) _litmus_P4_6_: addi 10,10,-1 _litmus_P4_7_: Lit__L9: _litmus_P4_8_: cmpwi 10,0 _litmus_P4_9_: bgt Lit__L8 _litmus_P3_0_: b Lit__L7 _litmus_P3_1_: Lit__L6: _litmus_P3_2_: li 11,1 _litmus_P3_3_: stw 11,0(28) _litmus_P3_4_: lwsync _litmus_P3_5_: lwz 31,0(8) _litmus_P3_6_: addi 10,10,-1 _litmus_P3_7_: Lit__L7: _litmus_P3_8_: cmpwi 10,0 _litmus_P3_9_: bgt Lit__L6 _litmus_P2_0_: b Lit__L5 _litmus_P2_1_: Lit__L4: _litmus_P2_2_: li 11,1 _litmus_P2_3_: stw 11,0(8) _litmus_P2_4_: lwsync _litmus_P2_5_: lwz 31,0(28) _litmus_P2_6_: addi 10,10,-1 _litmus_P2_7_: Lit__L5: _litmus_P2_8_: cmpwi 10,0 _litmus_P2_9_: bgt Lit__L4 Test W08 Allowed Histogram (1 states) 1 :>0:r3=1; 1:r3=1; 2:r3=1; 3:r3=1; 4:r3=1; 5:r3=1; 6:r3=1; 7:r3=1; No Witnesses Positive: 0, Negative: 1 Condition exists (0:r3=0 /\ 1:r3=0 /\ 2:r3=0 /\ 3:r3=0 /\ 4:r3=0 /\ 5:r3=0 /\ 6:r3=0 /\ 7:r3=0) is NOT validated Hash=1ccba20aa79d118a6a89b801f0499feb Observation W08 Never 0 1 Time W08 28.15 Revision 6766, version 3.00+1 Parameters #ifndef SIZE_OF_TEST #define SIZE_OF_TEST 1 #endif #ifndef NUMBER_OF_RUN #define NUMBER_OF_RUN 1 #endif #ifndef AVAIL #define AVAIL 1 #endif /* gcc options: -D_GNU_SOURCE -Wall -std=gnu99 -O -m32 -pthread */ /* barrier: user */ /* launch: fixed */ /* cache: false */ /* call: false */ /* affinity: incr0 */ /* randomise_affinity: false */ /* prealloc: false */ /* memory: direct */ /* safer: false */ /* preload: false */ /* para: self */ /* speedcheck: false */ /* proc used: 1 */ GCCOPTS="-D_GNU_SOURCE -Wall -std=gnu99 -O -m32 -pthread" LITMUSOPTS= mer jan 19 11:18:31 CET 2011